This invention relates generally to digital encoders and, more particularly, to digital encoders such as differential phase shift keyed (DPSK) encoders used in communication systems. DPSK is a class of modulation techniques that encode information as a carrier phase difference between successively transmitted data symbols. In encoding a stream of bits (having values 1 or 0), a conventional DPSK encoder modulates the phase of a radio-frequency or optical carrier in accordance with the binary values in the data stream. Typically, the carrier phase is modulated by switching it between two possible phases, 0° and 180°. Thus, the carrier phase is switched back and forth between two possible relative phases, or polarities. In binary phase shift keying (BPSK), the carrier phase is toggled back and forth in accordance with the binary values of successive bits in the data stream. BPSK has a well known drawback in that recovery of the carrier at a receiver is subject to a possible phase error of 180°. This drawback is overcome by the use of differential phase shift keying (DPSK). In DPSK encoding, the carrier phase is made a ‘1’ only if the next data bit to be encoded has a polarity that is different from that of the previously transmitted bit. Thus, if a ‘1’ bit has just been transmitted and another ‘0’ bit appears in the data stream, this latest bit in the data stream will be transmitted as a ‘1.’ But if a ‘1’ bit has just been transmitted and another ‘1’ appears next in the data stream, this latest bit will be transmitted as a ‘0.’ DPSK is sometimes defined as a modulation technique in which the carrier phase is changed each time a ‘1’ bit is transmitted and does not change phase each time a ‘0’ bit is transmitted.
DPSK is best defined from the logical equation:Qn+1=Dk ⊕ Qn, where n=0, 1, 2, 3 . . . and k=0, 1, 2, 3 . . .                and where Q is the encoded bit, D is the data bit and ⊕ represents the exclusive-OR function.        
Therefore, as shown in FIG. 1, the DPSK encoding function is conveniently implemented using an exclusive-OR (XOR) gate 10 and a flip-flop 12 to store the output of the gate and provide an output of the encoded bit Q. The Q output is fed back as a second input to the XOR gate 10, to compute the next Q output in accordance with the above equation. The output stream of encoded bits emerges from the encoder at the same bit rate that the data stream is clocked into the encoder. Unfortunately, in spite of its simplicity, this conventional DPSK encoder is often a “bottleneck” component that limits the rate at which a data stream can modulate a carrier using the DPSK modulation scheme. Time delays inherent in operation of the XOR gate 10 and the flip-flop 12 determine an upper limit to the rate at which the data stream may be encoded. Since encoding in accordance with the well known equation above is the very essence of DPSK encoding, there has always seemed to be no way to avoid using the conventional DPSK encoding structure of FIG. 1.
It will be appreciated from the foregoing that there has long been a need for an encoding circuit that avoids the potential bottleneck presented by the conventional DPSK encoder structure. The present invention satisfies this need, and provides a solution that has application to other coding schemes as well.